UltraLogicTM High-Performance CPLDs

• In-System Reprogrammable (ISRTM) CMOS CPLDs —JTAG interface for reconfigurability —Design changes don’t cause pinout changes —Design changes don’t cause timing changes • High density —32 to 512 macrocells —32 to 256 I/O pins —5 Dedicated Inputs including 4 clock pins • High speed 222 MHz in-system operation —tPD = 5 ns —tS = 2.5 ns —tCO = 3.5 ns • Simple timing model —No fanout delays —No expander delays —No dedicated vs. I/O pin delays —No additional delay through PIM —No penalty for using full 16 product terms —No delay for steering or sharing product terms • 3.3-V and 5-V versions • Fully PCI compliant[1] • Bus Hold capabilities on all I/Os • Intelligent product term allocator provides: —0 to 16 product terms to any macrocell —Product term steering on an individual basis —Product term sharing among local macrocells • Flexible clocking —4 synchronous clocks per device —Product Term clocking —Clock polarity control • Consistent package/pinout offering across all densities —Same pinout for 3.3-V and 5-V devices —Simplifies design migration across density • Security bit and user ID supported • Packages —44 to 352 pins in PLCC, PQFP, TQFP, and BGA packages • Warp2 —Low-cost IEEE 1076/1164-compliant VHDL system —Available on PC, Sun, and HP platforms for $99 —Supports all Cypress Programmable Products • Warp2SimTM adds: —Capabilities of Warp2 and Viewlogic’s ViewSim —Dynamic timing solutions for all Cypress PLDs • Warp3 CAE development system adds: —VHDL input —Viewlogic graphical user interface —Schematic capture (ViewDrawTM) —VHDL simulation (SpeedWaveTM)